CSS Mixed Signal ASIC Solutions

We are pleased to announce that Micro West Sales now represents Custom Silicon Solutions in the Southern California area.  Micro West Sales was founded by Irv Landrey in October 2011.  The staff now consists of five field representatives and one inside sales representative.

Irv Landrey has 35 years experience in the electronics industry.  His experience in sales and marketing of Integrated circuits is well known to many at CSS due to his prior work as Sales Manager at the Hughes Microelectronics Division in Newport Beach (The founders of CSS, Keith Shelton and Frank Bohac, were with that Hughes Division during Irv’s tenure).    At that time, Irv was responsible for both internal and external sales and hence has an excellent knowledge of the potential ASIC customers in Southern California.  Irv covers accounts in North Orange County and LA County.

Joining Irv as a sales representative is Mark Meeks.  Mark also previously worked at the Hughes Microelectronics Division, leading the marketing effort for Custom Gate Array ASICs.  Following Hughes, Mark greatly expanded his experience in the semiconductor industry at both Toshiba America and CMD Technology.  Mark covers accounts in South Orange County and North San Diego County.

Bob Smith has been a manufacturing representative for over thirty years and joined Micro West Sales in November 2011.  He has extensive experience working in the Southern California area in all type of RF, microwave and millimeter wave components.  Bob covers all accounts in North LA, Ventura and Santa Barbara Counties.

Rosemary (Rosi) Berliners has sixteen years of experience in sales and account management of electronic components prior to joining Micro West Sales in November 2011.  Rosi has been involved with sales of a wide variety of electronic components, including PCBs, Memory Modules and other Value Added Services in both Medical and the Military/Aerospace markets.  Rosi covers accounts in South Orange County and San Diego County.

Myles Cupp has been in sales for over five years.  He is also working on a BSEE at Fullerton State University.  Myles is VP of the Tau Beta Pi Engineering Honor Society and active as a Senate Member/Board Member at Fullerton College.  Myles covers all the universities and colleges in the Southern California area.

Jeanie Meeks also has experience at the Hughes Micro Electronics Division.  At Hughes, Jeanie led the program management effort that developed Custom Gate Arrays (ASICs) for the Hughes Missile Systems and Radar Systems Group.  She followed that with 15 years experience in electronic component distribution at Analog Devices.  Jeanie is the Micro West Sales inside sales manager.

We at CSS, feel that this team at Micro West Sales has the experience and contacts to successfully promote CSS custom ASIC sales in the Southern California area.  Please feel free to visit the Micro West web site at www.MicroWestSales.com or give them at call at 949-633-0979.

I read an interesting article recently discussing the advantages of Custom Analog ASICs.    It was an excellent article and it pointed out something I had not previously considered.  In a previous Blog, I discussed the advantages of a Mixed-Signal ASIC (Analog & Digital combined on a chip) and the advantages that I suggested were also included in the article – lower cost, saving space, improved reliability, better performance and improved reliability.   The author pointed out that his company does “REAL” Analog design – meaning full custom analog design – as opposed to a company that does “mixed-signal” design because they use analog functions from a cell library.

I agree that “REAL” analog design (full custom) could have significant advantages over a limited cell library of analog functions.  It had just never occurred to me that “mixed-signal”  design houses were thought by some to do their analog designs only with cell library functions.

So, I want to point out that Custom Silicon Solutions does “REAL” analog design in our mixed-signal chips.  We tailor our analog designs to meet our customer’s needs.  Typically this means that we have a combination of standard analog cells, modified analog standard cells  and full custom analog designs.  We feel this gives us the best performance at the lowest cost.

Custom Silicon Solutions was again invited to attend the ON Semiconductors Executive Conference in Scottsdale, Arizona.  This annual event provides an opportunity for ON’s major customers to meet one-on-one with ON Executives and discuss how to work together more productively.  The 4-day event consisted of the Executive Presentations, the General Session and the Market Segment & Application Session along with Individual Breakout Sessions with each company attending.
The Executive Presentations & Dinner was highlighted by presentations by Keith Jackson, President, Chief Executive Officer and Director, Bob Mahoney, Executive Vice President, Sales and Marketing, and David Somo, Vice President, Corporate Marketing.  The presentations were followed by questions from the floor.
The General Session highlighted updates from the ON’s Business Unit Directors.  This was followed by the Customer Breakout Sessions and Market Segment Presentations.  The theme for this year’s event was: “Partnering to Win in a Volatile Environment”.  We felt this theme was apparent in the presentations and especially in our Breakout Session.
A golf tournament was held to round-out the experience.  ON hosted the scramble event at the Gainey Ranch Golf Club.  The tournament was well attended and fully enjoyed by all.  CSS was represented in the following foursome by Keith Shelton, CSS President (second from left) and Mike McDaid, CSS Director of Sales (second from right).
As a special treat following the meetings, ON hosted the opening day at the Phoenix Open at their corporate tent on the 9th green.  Beautiful weather and an excellent lunch at the tent made this a memorable experience.

Over the past few months, CSS has been developing a new mixed-signal ASIC for Epitel*, Inc.  One of the striking aspects of this development is the match between Epitel’s needs and the some of the unique design capabilities of CSS.   We specialize in very low power instrumentation ASICs and EEPROM technology and these specialties are  just what was needed.

The ASIC consists of programmable gain amplifiers, an analog multiplexer, a clock generator, a 128 bit EEPROM and a programmable timer circuit.  The ASIC is designed for very low power operation (battery operation)  and includes  a sleep mode for ultra-low power consumption.  The EEPROM is used for configuration control, to calibrate the analog circuits and to store a serial number.  The ASIC will be packaged in a custom DFN package to further the miniaturization process.

*Epitel is a medical diagnostic device company that has invented and will soon produce a game-changing technology.  They are developing miniature telemetric recording systems for small animal models of human disease, with its first focus on diagnostics for epilepsy.  Continuous monitoring and miniaturization will revolutionize the understanding and treatment alternatives in that field. The miniaturized Epitel system overcomes the difficulties of “tethered systems” and allows for continuous monitoring for long periods of time.  The mixed-signal ASIC is a key component in this new technology and provides the capability for miniaturization.

Mike Receives the CSS 2011 ISO 9001:2008 Certificate

CSS successfully completed our annual audit for ISO 9001:2008 on July 9, 2011.  Pictured above on the left is Mike McDaid, CSS Director of Sales, receiving the certificate from Paul Wenger, Business Manager with ISO Management Systems.  This begins our third year using our Quality Management System (QMS) and we feel that the system has been helpful in maintaining quality in all we do – the design, production and delivery of custom mixed-signal ASICs.  Over the past two years, we have added a significant number of detailed Work Instruction to our QMS.  We feel these Work Instructions greatly assists us in consistently delivering quality products and services.

Since we specialize in mixed-signal ASIC designs, Analog-to-Digital Converters (ADC) are common elements in many of our projects.  In basic terms, an ADC converts the value of an analog signal (usually voltage or current) to a digital value that is proportionate in scale to the analog signal.  Probably the most common differentiator of ADCs is the level of resolution which is expressed in terms of bits (i.e. 8bit, 10bit, 16bit, etc.).  What the number of bits refers to is the number of unique binary values the ADC can produce over the range of analog values.  For example, an 8bit ADC can encode an analog input to one in 256 different levels (2⁸=256) and a 24bit ADC can encode an analog input to one in 16,777,216 different levels.  With such high resolutions, 24bit ADCs are commonly used in sensitive applications such as test and measurement equipment and high-end communications equipment.

So how does an ADC work?  In reality, there are several different ways you can go about converting an analog signal.  One way is by using a Successive Approximation approach.  A Successive Approximation ADC (SA-ADC) uses a comparator to evaluate the input value relative to a reference value generated by an internal Digital-to-Analog Converter.  The results of the comparison are then stored in an internal Successive Approximation Register (SAR).  When I was first trying to understand how a Successive Approximation ADC worked, the following analogy made things a lot clearer:  If I told you to guess a number between 1 and 48 and I will tell you if the number I’m thinking of is either higher or lower than your guess, the rational approach would be for you to guess 24.  If I said the number I am think of is higher than 24, your next guess would be 36 (half the difference between 24 and 48).  If I told you it was lower than 36, your next guess would be 30 (half the difference between 36 and 24) and so on until you were able to determine the actual number.  Using that approach, an 8bit SA-ADC would make the comparison 8 times with each successive comparison based on a reference value that is half the difference of the narrowed range.  If the input value is lower than the reference value, the return is a 0.  If the input value is higher than the reference value, the return is a 1.  The result of each of these comparisons is subsequently stored in the SAR.

In order to be able to quantify the actual resolution, one must first know the range of input values and the resolution of the ADC in bits.  Using the following formula:

Q= V_Refhi – V_Reflow

2^N

Where Q is equal to the resolution or value per step, V_Refhi is equal to the highest possible value of the input voltage, V_Reflow is equal to the lowest possible value of input voltage and N is the ADC’s resolution expressed in bits.

Using this equation, we can determine that with an input voltage that ranges from 2.2V to 2.8V, an 8 bit ADC can convert the input voltage with an accuracy of .0023V or 2.3mV.  A 16bit ADC can convert the input voltage with an accuracy of .00000916V or 9.16μV.

There are two reasons why I like people asking me questions.  First, I like to help people broaden their own level of knowledge.  I may have missed my calling as a formal educator but being in sales, I’m constantly presented with opportunities to help people better understand our industry and technology.  The other reason I like being asked questions is that when I don’t have the answer, I’m compelled to figure it out. This in and of itself, helps me to broaden my own knowledge base.  Over the next couple of blogs, I plan to discuss at a fairly high level some of the common elements of analog/mixed-signal ASICs.  If there is something in particular you would like me to cover or you would like more in-depth information pertaining to one of the topics, let me know.  I’m confident that while I’m helping you, I’ll also be learning a thing or two myself.

Having successfully completed several mixed-signal ASIC designs targeted for medical device applications, we quickly recognized that this market segment held plenty of opportunity for us but we were not adequately addressing the demand.

As a result, we began to put together a marketing plan designed to help build some name recognition within the medical device community as well as communicate our value proposition as an analog and mixed-signal ASIC designer.

As part of that plan, we signed on with Qmed as a qualified supplier and are now in the process of putting together a strategic marketing campaign to target their user base of over 350,000 medical device professionals worldwide.

If you are in the medical device industry, particular in the design function, you may want to take a look at the resources they offer and register to receive any of the e-newsletters they regularly send out that are targeted toward your specific discipline.  Among others, I subscribe to their Qmed Daily and I’m impressed with their consistent reporting of the latest goings on in the medical device industry.

As we have touched on in the past, two key considerations to be factored into your decision on whether or not to move forward with developing a mixed-signal ASIC are how much it will cost and how long it will take to complete the project.  In our world of “time equals money,” logic dictates that the quicker you can get the design done, the less expensive it will be.  In an effort to help save you time and thus money, here are a couple of things to keep in mind as you get ready to engage with an ASIC development partner.

1. Know Your Target Before You Pull the Trigger

Nothing kills a development schedule quicker than a moving target.  Bear in mind that we typically will be involved in helping our customers define their final specification.  However, that process is undertaken BEFORE any design work begins.  In general, we don’t provide a firm quote until the final specifications are set.  This helps to prevent “migrating requirements” and the resulting late deliveries and cost overruns.

2. Overkill Kills

As fundamental as this sounds, try to minimize any design requirement overkill.  We commonly find that ASIC specifications are written based on the discrete IC’s used to develop a working prototype.  This may seem logical but it’s not uncommon to have specs written that are well beyond the requirements of the application.  Do you really need a 16bit ADC or will a 12bit version work fine? Is it absolutely necessary to squeeze those last few milliamps out of your operating current spec?  Before finalizing your specification, be sure you understand where you set the bar and why.  Otherwise you may be unnecessarily adding weeks to your schedule and tens of thousands of dollars to your budget.

3. Chose a Design Partner with Relevant Expertise

If you are looking to develop an analog or mixed-signal ASIC, it is important that you engage with a design partner that has relevant experience with the “art” of analog design.  A couple of our engagements have come out of the ashes of attempted mixed-signal designs gone poorly at other design companies.  We were ultimately able to deliver to the customer what they wanted but the “do over” resulted in significant schedule delays and at a total cost that exceeded what was initially anticipated.  Before engaging, ask your design partner about experience they have had with similar designs/technologies/applications.  If you still have questions, don’t be afraid to ask for references so you can get another customer’s perspective.

4. Don’t Unnecessarily Pressure the Process

Although this is the inverse of the “time equals money” principle, if your internal target for samples is August 1^st, you probably shouldn’t ask for samples to be delivered June 15^th.  Compressed schedules result in additional costs to your design services partner (both hard and opportunity) which ultimately will be passed on to you.

Did I miss anything?  Let us know what experience has taught you about meeting schedules.

In considering how to integrate your electronic system, you could consider an ASIC (Application Specific Integrated Circuit) or a FPGA (Field Programmable Gate Array).   To make the best choice, the benefits and shortcomings of each technology need to be understood as they relate to your needs.

If you are the design engineer, the required circuit performance is a top concern, as well as the tools and skills you would need to successfully complete the design.   Costs are going to be a key consideration, especially for your company’s financial and program managers.  These costs would include both development (nonrecurring engineering (NRE)) and production (recurring unit cost).  Finally, time-to-market may be very important – to everyone, but probably especially so for marketing people.   So, to be successful, your approach needs to meet the needs of everyone involved.

First consider the question of costs.  The top level answer to that question is that ASICs will cost more to develop, but cost less to produce.  This usually means that FPGAs are more cost effective for lower volume applications and ASICs are better for higher volume applications.  To determine financially if an ASIC is best, you just need to determine at what volume the total cost is the same.  After that volume, you will begin to save money with the ASIC.

An example is useful.  Assume that for a large ASIC design at CSS, the NRE is $200,000, the FPGA and analog circuits it replaces cost $40 and the ASIC unit cost is projected to be $20 (you are saving $20/unit).  Further, your expected volume is 10,000 units annually for the next 5 years.  Referring to the chart below, the  break-even point (when your savings equals your NRE) occurs in one year after start of production and you will be saving $200,000 for each year to follow.  If you find that for your application, it takes too long to recover the ASIC NRE, an approach often taken is to implement first in a FPGA when volumes are expected to be low, and then convert to an ASIC when the application is successful and the volumes become larger.

Next consider the time-to-market.  An ASIC will usually take considerably longer since, in addition to the design, it needs to be fabricated from scratch and debugged.  This time can typically be 6 to 12 months from design to full production.  An FPGA typical development time can be shorter, since the devices do not need to be fabricated and last minute changes can be implemented in a shorter time.

The ASIC development time can be shortened if the ASIC design house has most of the basic cells needed available in a library (usually true for digital circuits and many of the analog circuits).  At CSS, we have a large library of both digital and analog cells, so often times the circuits just need to be configured to the application.  Many times all that is required is to optimize existing cells to meet specific requirements (power, speed, etc.).
FPGAs are sometimes used in an ASIC development as the first step of the ASIC design.  This is especially true if the digital design is complex or is not yet well defined.  By designing this digital part of the circuit in an FPGA, it can be fully evaluated, often in the intended application, before committing to the custom ASIC version.

Closely related to cost, is the degree to which your system can be integrated.  ASICs here have an advantage if you need analog circuits in your system.  Mixed-signal ASICs by definition have both analog and digital circuits available which can probably meet your design needs.  FPGAs with any significant analog circuitry are not available.  So an ASIC makes it possible to implement your design in a single chip, which is less expensive and takes up less board space.

Finally, consider circuit performance, design tools needed and the skills required.  Design tools for FPGAs are typically available at no cost from the FPGA manufacture, at least for the digital part of the circuit.   Although there is a learning curve, the skills needed to design the digital circuit on a FPGA can be learned by a competent designer.  The same designer may be able to find separate analog ICs to complete his circuit.   On the other hand, a mixed-signal ASIC design house will have all the tools and expertise to complete both the digital and analog designs in a single ASIC.  Often, the experience of the design house, along with their library of existing digital and analog cells, will considerably shorten the design time.  At CSS, we can provide a turn-key design service, relieving our customer of that significant responsibility – often in a shorter time than it would take to implement an FPGA design.