My last input here briefly described the CSS555 Timer Component Calculators and the one before that was on the CSS555 EZ Programmer. Determining how to program the Timer and establish the external components are essential steps in a board level design. The next step for a designer using the CSS555 Timer is the board level circuit simulation. To assist this task, CSS provides a simulation model that can be used in a SPICE circuit simulator.
This SPICE model is designed to accurately model the characteristic of the CSS555 Timers and still keep simulation times quite reasonable. The model includes simulation of the supply current (over Vdd), inputs switch levels, propagation delay time, output drive (over temperature and Vdd) and ESD clamp diodes and pad capacitance. The following shows a simulation of the Timer with the P-SPICE Simulator.
A complete and detailed explanation of this SPICE model for the CSS555 is available for download on the CSS website on the Standard IC Products page. This detailed explanation is found in the application note CSS555C_App_Note2_SPICE_Model.pdf. The text that may be used as an input to SPICE to describe the model is also available for download on the same website page (CSSS555C_SPICE_ Models.txt).
I would like to encourage anyone anticipating using the CSS555 in a board level simulation to try out this model and let us know what you think. I would also like to thank Jim Granville who has been very helpful in debugging this model and has made significant contributions for recent improvements.