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The Engineers of CSS – Allan Stewart

November 11th, 2014 by Keith
The Engineers of CSS – Allan Stewart

CSS has a great staff of engineers, but since they are often working “behind the scenes” they may not be well known outside the Company. This Blog, featuring Allan Stewart, is a continuation in the series of interviews titled “The Engineers of CSS” which will hopefully help everyone to know them much better.


Allan Stewart

Here is a little bit about Allan in his own words.

I graduated with a BSEE  for the University of Strathclyde, Glasgow Scotland in 1975 and began working as a circuit design engineer for Telecommunications, Defense, and Medical companies in the UK.  I joined Burroughs/Unisys in 1984 to work on circuit board development, and transferred to Orange County to take up a circuit design manager position in1987.  I joined Adaptec in 1996 responsible for Disk Drive servo controller ASIC development, and moved on to TI Storage Products where I also became involved in Disk Drive Read channel development.  I joined Calimetrics as Director of ASIC development in 2000 – working on multi-level CD and DVD technology development storage products.  I became an independent consultant in 2003 working on a number of projects developed jointly by Treehouse Design in Colorado and Chronicle Technology in Irvine.  I began working exclusively for Chronicle starting 2011, initially developing a 1.5Gbs SerDes interface for High Speed Video applications, and latterly worked on the 65nm and 28nm Bitcoin devices for Butterfly Labs.


CSS: You have a very impressive background as indicated in your history as provide above. What were the most interesting or technically challenging projects you have worked on during your career?

Allan:  From a technically challenging perspective I did a 1.5 – 2.5 Gbit/s SerDes with Chronicle just prior to the 65nm bitcoin chip, which was quite challenging. It combined high frequency PLL work along with some high speed digital requirements, allowing me to re-visit some of my old circuit board design challenges from earlier in my career.

CSS: You started working at Chronicle Technologies prior to the merger of Chronicle and CSS in 2013. What do you feel have been the advantages of the merger?

Allan:  I think the benefits were the result of each group having different strengths in terms of the depth of their capability.  Chronicle had more depth in design and layout, CSS brought the production test capability and ISO certification.  The result was not a significant overlap in skills and a good combination of the skills for ASIC design, test and manufacturing.

CSS: I know that you were a key person in the recent development of the bitcoin chips. Both the 65 nm and the 28 nm chips were successful complex digital designs. The 28 nm chip was an especially large ASIC, with 5.5 billion transistors!   What do you remember most about these developments?

Allan:  The 65nm was probably the more difficult of the two designs.  We had to figure out the architecture – we experimented with 5 or 6 different technologies trying to get the combination of speed and power we desired.

The test development was a challenge also – this was really the first time CSS and Chronicle had worked closely together – so it was a learning experience – but in the end I think a very successful one.

From a design perspective, the 28nm was more straightforward. We identified & designed the cells that needed to be improved to meet our new targets.  However. since this chip increased the number of Hash Engines from 16 (on the 65nM design) to 1024, it was huge and consumed 350Watts power.  These were the challenges.

Test results were excellent. Power was significantly lower and the operating frequency significantly higher than projected. We spent a lot of time estimating parasitic effects and these results were now showing it had been time well spent.

CSS:  Do you have any spare time for hobbies or other activities outside of work?

Allan:  Soccer is my main pastime, although I enjoy baseball in the soccer off-season. My preference would be to be still playing soccer, but a combination of injuries and the passing of time means I have to content myself with just watching now.


Nanium Develops Advanced Package for CSS

November 11th, 2014 by Keith

Nanium S. A. recently published a Press Release regarding an advance package they developed for CSS:

“Nanium S.A. has unveiled what the company believes is the industry”s largest Wafer-Level Chip Scale Package (WLCSP), a 25x23mm packaging solution produced in volume on 300mm wafers.  Entirely developed in-house for Custom Silicon Solutions (CSS), a California-based provider of complex mixed-signal ASIC solutions, the customized Fan-In Wafer-Level Packaging/ WLCSP solution is nine times larger in area than the industry standard WLCSPs, typically measuring up to 8x8mm.


The Nanium Chip Scale Package Developed for CSS

“After completing a very successful high volume run of a 65nm product in eWLB at NANIUM, we approached them with our next 28nm WLCSP requirements. The first article worked as promised and enabled CSS to get to market quickly with an ASIC unprecedented in thermal and computational performance”, said Mike McDaid, Director of Sales at CSS in a statement.

“No other package solution in existence would have achieved the low lead resistance and high reliability we demanded. This ASIC in Nanium’s WLCSP establishes a new world class of integration, beyond VLSI-SOC (Very Large Scale Integration System-on-Chip). The final product is just about the maximum reticle size allowed and consumes hundreds of Watts!” McDaid added.

The wafers with the high-performance digital chips are produced with 28nm CMOS technology and contain over 5.5 billion transistors, one of the largest transistor-count chip produced by Global Foundries. Once produced in Dresden, Germany, wafers are sent to Nanium for packaging.

The WLCSP solution developed by NANIUM relies on a high count of 1,188 solder balls at a wide BGA pitch of 0.7mm. It has successfully passed more than 400 temperature cycles on board.