CSS Mixed Signal ASIC Solutions

CSS became ISO 9001: 2008 certified on July 1, 2009. We have been working over the past year to achieve this important milestone.  Everyone at CSS worked hard to make it happen.  I think we all believe that the systems that are now in place will help us to better serve our customers.  We have also found that the sytems make our job a little easier - by formally putting in place the necessary processes to get the job done.

Robert Shackelford, CSS Quality Manager, was the key person at CSS working to accomplish this goal.  Robert is shown below with Derek Luffman, Certified Lead Auditor, with IMSM, on July 1, 2009, following our successful audit.

Derek Congratulates Robert

Micro-power 555 Timers

Custom Silicon Solutions (CSS) is introducing a new version of the popular 555 Timer IC.  It is pin-for-pin compatible with the original 555 Timer, but by applying an advanced, mixed signal process, we have cut its power by over 10X and have added programmable features to this classic circuit.  It can still be configured to mimic a standard 555 timer, but with its internal timing capacitor and programmable six-decade counter, it can do much, much more.  And, despite all these features, the same eight-pin configuration has been maintained – thanks to a small, built-in EEPROM that stores configuration data.

555 Timer History

The original 555 timer was designed by Hans Camenzind at Signetics in 1970.  Its part number was derived from the three 5KΩ resistors that provide the 1/3 x VDD and 2/3 x VDD trip levels.  It contained about 15 resistors and 25 transistors and drew ~3mA at 5V.  In contrast, our CSS555C device contains over 2000 active and passive circuit elements and draws less than 5uA at 5V.  The 555 timer is one of the most successful and long lived IC’s of all time.  About a dozen manufacturers still produce bipolar and CMOS versions.  Almost 1 billion devices are still sold each year!

A block diagram of the original 555 timer IC is shown below.  It consisted of a resistor divider, two comparators, a flip-flop and two output devices.  Its simple architecture made it extremely flexible.  It has been used in a wide range of applications, too numerous to list.  Entire books can be found that are entirely devoted to application circuits for the 555 timer.

                                                                  Original 555 Timer Circuit

Goal #1 – Reduce Power

One of the goals for our CSS555 timer was to reduce the supply current to below 5uA.  We drew from circuits originally developed for battery powered utility meters and implantable medical devices.  Both applications required micro-power mixed signal ICs.  The result is a new 555 timer that draws 10X less current than any other 555 IC.  A comparison of seven low power 555 timers is shown in the table below.

Goal #2 – Make Long Delays Easy to Generate

A second goal for the new CSS555C was to make it easier to generate long delays.  The original 555 timer required a large RC time constant to accomplish this.  Large capacitors have several drawbacks: high price, poor accuracy and wide variation over temperature.  The CSS555C includes an internal six-decade programmable counter that effectively multiplies the value of the timing capacitor by the counter setting.  It provides seven multiplier settings: 1, 10, 100, 10³, 10⁴, 10⁵ and 10⁶.  Accurate delay times, from milliseconds to days, are easily implemented with small sized capacitors.

Goal #3 – Provide an Accurate Internal Timing Capacitor

The internal counter eliminates the need for a large value timing capacitor.  It would be even better to eliminate the capacitor altogether.  The CSS555C does that!  A 100pF capacitor has been integrated into the IC.  It features a low temperature coefficient (TC < 100 ppm/°C) and ±1% accuracy.  It is factory trimmed, but can be re-trimmed (electronically) after PCB assembly.  (This allows errors in the timing resistors to be compensated for by trimming the internal capacitor.)

Goal #4 – Reduce the Minimum Operating Voltage, Maintain Speed & Accuracy

Two additional analog settings have been included to increase the flexibility of the device.  The trip levels can be changed from the traditional 1/3, 2/3 to 10% and 90%.  The wider trip levels extend the minimum operating voltage down to 1.2V.  The power level can be increased for applications that require higher speed and/or accuracy.  (Increasing the power level speeds up the comparator response time.)

Goal #5 – Maintain the Standard 8 Pin Configuration

For most timer applications, the CSS555C can be used as a direct replacement for the standard 555.  An internal EEPROM holds the configuration data and capacitor trim setting.  A serial interface, using existing pins, is designed to maintain the standard pin count and functions.  A block diagram of our new CSS555C timer is shown below.  It still has the same basic elements (and 8 pins) of the original 555, but we’ve added some great new features.  A detailed specification can be downloaded from our website and a Demonstration Kit is available to make evaluation of the new IC quick and easy.

                                                        Advanced CSS555C Timer Circuit

For more information, contact us at (949) 797-9220

Pat Fitzpatrick has joined the CSS Sales Team.  Pat has over 20 years of sales experience.  Over the years, he has held a number of positions, including Sales Engineer, Account Manager and Field Applications Engineer and Regional Sales Manager.  With this experience, Pat has been able to quickly learn about the CSS products - both our Custom ASICs and our Standard IC Products.

Pat has the ability to meet customer needs by understanding the customer requirements and how our products can satisfy those requirements.  We anticipate that you will be hearing from him soon in his new assignment at CSS. 

Pat is in the process of completing his MBA through the University of Phoenix.  Earlier in his career, he spent four years in the U.S. Marine Corp reaching the rank of captain.

Most of our mixed signal ASIC designs benefit greatly by including the ability to trim key analog circuits.  These often include an amplifier gain/offset, a bandgap reference voltage, a bias current generator or the frequency of an oscillator or filter.  A small amount of nonvolatile memory, coupled with an array of FET switches, resistors and capacitors can provide the equivalent of a discrete DIP switch, trim pot or trim capacitor.  An integrated version of these components also has the advantage of providing electronic trimming.

The most versatile type of memory for storing a trim setting is an EEPROM (Electrically Erasable Programmable Read Only Memory).  As the name implies, it can be written and erased electrically and therefore allows a trim setting to be changed numerous times, either at device test or in the application circuit.  A conventional EEPROM contains a memory core, surrounded by peripheral circuits (row/column drivers, sense amps, etc.).  It may require significant die area and special process steps, both of which may drive the cost of the IC to unacceptable levels.  What’s really needed for holding a trim setting is a small, efficient EEPROM that does not significantly impact cost.

Our nonvolatile registers provide an ideal solution for storing trim settings.  The core memory circuit is a self-contained, nonvolatile latch (NV Latch).  Each NV Latch includes its own level shifter and sense amp, so they can be distributed anywhere they are needed.  They automatically power up to their last programmed state and draw essentially no static current (just junction leakage current – typically less than 1nA).  They can be mated to a wide variety of digital interface circuits to provide serial and parallel read/write access.

Our NV Latch cell does not require any special processing during wafer fabrication, so including it in a design does not add processing steps (or cost).  Even though each bit is completely self-contained, it is still a very area efficient memory.  In the table below, the area required for conventional and latch based EEPROMs are listed.  As expected, when a large number of bits are required, a conventional EEPROM is the densest configuration.  For applications requiring less than several hundred bits, a latch based architecture can be much smaller (and flexible).  For example, a 16 bit NV register requires under 20 square mils or about 1.08 square mils per bit.  This is about the same density per bit as a 0.5K EEPROM, but can be added in 16 bit increments and distributed throughout the IC.  A conventional EEPROM typically has a minimum size of several hundred square mils, corresponding to 256 to 1K bits.  (As the number of bits is reduced, the peripheral circuits dominate the total area required for the memory, making very small memories impractical.)  When less than 100 bits are required, an NV Register can be more than 10 times smaller than a conventional EEPROM.

 EEPROM Area (Conventional vs. NV Latch)

If you are an IC designer and would like to explore the features of our NV Registers for your own design, you can download specifications for our “Classic” and “High Density” macro cells.  Calculators for our latch based and conventional EEPROMs are also available.  (These are interactive tools that provide EEPROM area estimates for different memory configurations.)  You can download specifications and calculators by visiting our “Products/IP Products” web page.  Look for “16K EEPROM”, “High Density NV Register” and “NV Register” (Classic Version).

Our library of NV Registers provide a very versatile memory for storing analog trim settings.  Because they require minimal area and no extra processing steps, they have little or no impact on part cost, but can significantly improve part performance.  (They often reduce cost by improving yield when a spec is tight.)  We have found these small EEPROMs so useful that almost all of our mixed signal designs use them.  In addition to storing trim settings, we often use them to save counter states (odometers), configuration data and part ID’s.  For more examples of typical applications, see our “Products/Applications Overview” web page.

Custom Silion Solutions, Inc along with other key customers was recently invited to ON Semiconductors Executive Meeting in Scottsdale, Arizona. Custom Silicon Solutions (CSS) has been a partner with AMIS (now ON Semiconductor) for over 13 years.

The attendees met to discuss the future stategies for the Integrated Circuit Industry. On Semiconductor executive V.P. Bob Mahoney set the tone of the conference with his statement: “What can we do to help you succeed”.

CEO Keith Jackson followed with challenges that the IC Industry is up against in these difficult economic times. Here at CSS we are using this time to build our Marketing and Sales department and aggressively pursue new business.

The V.P.’s from each business sector at ON Semi continued with the same flavor-how ON Semi is becoming a “solution solving” company by increasing their Field Application Engineers involvement with their customers.

At CSS, we have a similar slogan: “Custom Silicon Solutions is your Turn-Key Solution for Mixed Signal ASIC Development & Production”. We provide these mixed signal custom ASICs to the Industrial, Medical, Security, Sensors and Automotive markets.

In the break out sessions, I met with the sales team that handles our account. We worked together to establish ways in which we could strengthen the CSS-ON Semi partnership.

It was not all work. The best ball/scramble golf tournament and the day at the PGA FBR Open was a good opportunity to have fun and enhance business relationships.

Our ASIC customers are fully aware of all the advantages of mixed signal ASICs, but for those who have never considered one, this top-level review should be helpful. When compared to a system designed with Standard ICs, a mixed signal ASIC can reduce power, size and production costs and improve performance and reliability. The importance of these advantages varies with the application and your needs.

Power is often a significant consideration. Custom mixed signal ASICs can considerably reduce the power consumption of your electronic system. With power as a primary concern, the logic for a custom ASIC can efficiently be implemented in a state machine and avoid the power consumption of a microcontroller clock solution. Also, analog functions in a mixed signal ASIC can be optimized for low power operation, a feature not often available in Standard ICs. At CSS we find that system power can often be reduced to a small fraction of what it would be in a system built with Standard ICs.

On the other hand, speed may be more important than power. You have the option of a speed/power trade-off in the design of a custom ASIC. Or, perhaps noise is a critical issue in your design. The point is that with a custom mixed-signal ASIC, the characteristics most critical for your application can be optimized during the design of the ASIC.

Analog performance may also improve with a mixed signal ASIC. Here, CSS has a particular advantage. We have developed the capability to trim important analog functions using nonvolatile memory (EEPROM) cells built into the ASIC. For example, with this capability we can trim out production variations and set amplifier gains as needed to meet critical specifications.

Of course, an ASIC is much smaller than all of the Standard ICs that it may replace. So, if this is one of your requirements, a custom ASIC may be the only solution. You can further reduce size by selection of a small surface mount package, such as a QFN package. CSS has access to a wide variety of small packages and packaging facilities to meet your needs.

A custom ASIC will also improve your system reliability. The reduction in component count and their required interconnects at the board level provides for a significant improvement in reliability.

Finally, a custom mixed signal ASIC can significantly reduce your production costs. This is often the primary motivating factor for developing an ASIC. The production cost of a custom ASIC can be considerably less than the Standard IC components it replaces. In addition, the reduction in components will reduce the system assembly costs.

The downside of a custom ASIC often presented is that they are expensive and time consuming to develop. The development cost (NRE) of an ASIC should be compared to the savings it will provide in production. Our experience at CSS is that when a custom ASIC is compared to the Standard ICs it replaces, the development NRE can typically be recovered in a year of production savings.

Development time for a custom mixed signal ASIC is, of course, longer than the development time using Standard ICs. Development time depends on the complexity of the ASIC and the experience of the ASIC design team. CSS has extensive design experience in the development of custom ASICs. By using a proven development process and use of previously designed cells whenever possible, we are able to develop a custom ASIC in a relatively short time.

Finally, in considering the development of a custom ASIC, you need to consider how much knowledge of ASIC development is required and what internal resources are necessary for your development to be successful. Our customers are always pleased to find that they can acquire a mixed signal ASIC without the need to dedicate staff to the job or to cope with all of the technical aspects. We provide a turn-key ASIC solution.

March 1, 2009

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