CSS Mixed Signal ASIC Solutions

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your Mixed Signal ASIC Solution.

Audit 2013

Keith Shelton (CSS) and Richard Cornick (QAS International) at 2013 Audit

CSS successfully completed an annual audit for ISO 9001:2008 on June 28, 2013.  Pictured above on the left is Keith Shelton, CSS Quality Manager, with the auditor, Richard Cornick, from QAS International.  These annual audits are to assure the CSS is performing to the requirements of ISO: 9001:2008, but is also an opportunity to discover ways to improve beyond the basic ISO requirements.  Richard was very helpful in this regard by providing suggestions for improved internal auditing procedures and notes on how to audit our suppliers.  His comment in the audit report: “During the opening meeting and subsequent discussions with the management team it became very evident the primary focus (of CSS) is Quality and ISO Compliance”.  This comment was very much appreciated as it does reflect the CSS commitment.

This begins our 5th year using our Quality Management System (QMS) that was established in 2009 with the assistance of “International Management Systems Marketing Limited” (IMSM).  IMSM typically assists small companies, like CSS, to establish a QMS that fits their needs.  I feel that they did a great job helping us get the system set-up in timely manner and at a reasonable cost.

We feel that the system is necessary to maintaining quality in all we do – the design, production and delivery of custom mixed-signal ASICs.  The ISO 9001 Procedures, Forms and Work Instructions all work together by providing the framework for our work at CSS.


I attended the GSA (Global Semiconductor Alliance) Silicon Summit in Mountain View, California a while back which addressed “More-than-Moore” (MtM) developments.  It was an interesting meeting and had an excellent group of speakers addressing the subject.  In considering what to say about that meeting, I decided that general background information leading up to MtM would be helpful.  The White Paper “More-than-Moore” by Wolfgang Arden, and others, provides a wealth of information in this regard.  The following is my interpretation of some of the key background information items described in this White Paper.

The amazing development of semiconductor industry for the past decade and continuing today has been guided by the “International Technology Roadmap for Semiconductors” (ITRS).  This roadmap, essentially limited to digital functionalities development (logic & memory storage) is based on Moore’s Law (Gordon Moore observed that market demand and the resulting industry response for functionality per chip (bits, transistors), doubled every 1.5 to 2 years).  Using Moore’s Law and in particular by dimensional scaling as conceptualized by R. Dennard  (reducing dimensions while keeping electric field constant)  as a “technology push”, the ITRS has been able to identify the key industry developments necessary to sustain this very rapid growth of digital technology.  Known loosely as “More Moore” (MM) the scaling of digital IC’s has been able to continually improve performance-to-cost ratios of products and hence the exponential growth of the semiconductor market.

Essentially left out of this rapid growth in the past have been the functionalities which would add significant value to new products, but that do not necessarily scale according to Moore’s Law.  This led to the need for a “More-than-Moore” (MtM) development roadmap. These functionalities (sensors, actuators and powering products) are typically needed for the More Moore technologies (digital processing and storage) to interface with the outside world.   These functions imply analog and mixed-signal processing, passive components, high voltage components, micro-mechanical devices, sensors and actuators and micro-fluidic devices.  The Arden White Paper suggested that the ITRS community (the Technology Working Groups (TRGs) and the International Roadmap Committee) include the MtM domain in its work and then proposed a methodology to identify the feasible & desirable MtM technologies for such a roadmap.

The proposed methodology is different than that for More Moore technologies.  Moore More was a “technology push” based on Moore’s Law and Dennard’s scaling rules.  The proposed methodology for MtM is more “market pull” based.  The basic concept is to identify future markets that need the MtM capabilities and work back to the specifics of the technologies necessary to meet the market need.   In taking this approach, it would be necessary to assure that the development would also most likely enhance the development of other market needs and hence allow for accelerated growth.

An example cited was in the automotive market.  One of the products was an advanced power management and handling capable for CMOS low voltage circuitry. This would require innovation in power electronics and drive technical requirement for the underlying high voltage power technologies.  From this point, is should be possible to determine the technical requirements for key parameters on the technology module level – such as the on-state resistance specification (Ron) of the end unit control electronics.

Another example given was the “Radio Frequency and Analog-Mixed Signal Technologies for Wireless
Communications” TWG who have been roadmapping many devices in the RF space and in effect have pioneered the methodology described in the White Paper.

One of the sessions at the GSA Summit was “How More than Moore Impacts the Internet of Things”.  This session was chaired by Edward Sterling, Editor in Chief, System-Level Design and Editorial Director, Low-Power Engineering.

Although the concept of the “Internet of Things” (IoT) has been around for some time – the term was first used by Kevin Ashton in 1999.  I think the following quote from Wikipedia expresses both the concept and potential of the Internet of Things:  “If we had computers that knew everything there was to know about things—using data they gathered without any help from us—we would be able to track and count everything, and greatly reduce waste, loss and cost. We would know when things needed replacing, repairing or recalling, and whether they were fresh or past their best. The Internet of Things has the potential to change the world, just as the Internet did.”

Here are some of the points of discussion from this session that I felt were interesting:

  • Everything that can be connected (to some advantage) will be.
  • Once you get to the extremes – going out to the edge – power management will be key and mixed-signal technology will be much more important.
  • Need seamless, programmable local devices to enable communication.
  • Almost everyone could make money – instrumentation important
  • Chip Support:
    • Micro-controllers
    • Custom Chips
  • Standards will develop later – as soon as better understood
  • A Killer App example: Home thermostat aware of people present

A lot more information on IoT is available on the web.  I think “The Internet-of-Things Is About To Change Everything” in Beverly Macy’s Blog is especially informative.


Is Heathkit Back?

May 31st, 2013 by Keith


I read Doug Grant’s article regarding Heathkit in his Blog via the EDN Network.  Doug reminisced about building his first Heathkit and how much he learned.  He suggested that every EE had at least one kit and I suspect he is right.  However, as Doug pointed out, Heathkit eventually faded away.

I built a number of kits, including an oscilloscope, a solid-state FM tuner and amplifier and a color TV.  All worked fine and found lots of use.  But the real advantage was the first-hand learning experience & knowledge gained in building the kits.  The building instructions were always clear and the circuit operation explanations were my first real learning experience in electronics.  Just learning how to solder was a valuable experience!

Doug’s Blog provides a link to someone who may be considering offering the kits again and he also offers his suggestion for a new kit.  A lot of comments follow the Blog offering individual experiences with Heathkit and related suggestions.  I feel that they offered an excellent product for that time period and I am glad I had the opportunity to learn by building their kits.


An Artist Conception of the Solar Orbiter Spacecraft Orbiting the Sun Credit: NASA

CSS Engineers have teamed with Sarnoff/SRI in the design of a CMOS image sensor that is slated to be aboard the Naval Research Laboratory”s Solar Orbiter Heliospheric Imager (SoloHI).  This work is a continuation of a long teaming relationship with Sarnoff, having completed 16 earlier “tape-outs” of new designs.

The SoloHI”s detector is a 4K x 4K Advanced Pixel Sensor using CMOS technology, as shown below.


The 4K x 4K Advanced Pixel CMOS Sensor

This will be the first time such a large format APS detector has flown. The instrument will make high-resolution images of the corona and solar wind, including coronal mass ejections (CMEs), to determine how they propagate and interact with the background solar wind. With its large field of view, SoloHI will be able to connect the remote sensing observations of the corona to the plasma being measured in-situ at the spacecraft.

Read more at:


CSS555C Used in Guitar Tuner

April 11th, 2013 by Keith

I read a very nice review of an application of the CSS555 Timer IC by Steve Schuler from his BLOG Square_Root_of_Not.   Steve shows how to use the CSS555 Demo Kit to program the CSS555C to set the frequencies for a guitar tuner.  Check out the review on the science20.com website.

Custom Silicon Solutions (CSS) was again invited to attend the ON Semiconductors Executive Summit in Scottsdale, Arizona.   This annual event provides an opportunity for ON’s major customers to meet one-on-one with ON Executives and discuss how to work together more productively.

The event began Tuesday evening (January 29) with the ON Semiconductor Executive Overview & Dinner Meeting.  Speakers included Keith Jackson, President, Chief Executive Officer and Director, Bob Mahoney, Executive Vice President, Sales and Marketing, and David Somo, Vice President, Corporate Marketing.

The Customer Breakout Sessions (one-on-one discussions between ON Semi and Customer Executives) began on Wednesday.  CSS (now merged with Chronicle Technology) was represented by CSS Executives John Cheng and Mike McDaid.   ON Semi Executives included Rocke Acree (Custom Foundry Business Unit Manager), Mike Kenyon (Sales Director, Western US), Chip Brakeville (Regional Sales Manager, Southwest & Central US and South America) and “Abdi” Afshar (Field Application Engineer).

At the meeting, John Cheng discussed the benefits of the CSS/Chronicle Merger, including the significantly increased engineering staff and the additional production & testing capabilities of the combined companies.  Another topic of special interest was the development of EEPROM technology for the ON Semi ONC18 process (180 nM process at the ON Gresham facility).  CSS is developing this technology (design & evaluation) with ON providing silicon fabrication.   Test structures for EEPROM cells & associated circuits have been completed and are soon to begin fabrication at ON.  This will be followed by development of a complete EEPROM memory and the required on-chip programming circuits.

As a special treat following these meetings on Thursday, ON hosted the opening day at the Phoenix Open at their corporate tent on the 9th green.  John and Mike from CSS attended and were able to enjoy refreshments at the tent and then follow Phil Mickelson around the course in his near record breaking round.


Phil Mickelson Wins the Phoenix Open

Chronicle Technology has just recently completed ESD and life testing of its motion control ASIC, which now clears the path for production volume ramp-up. This custom designed mixed-signal ASIC is targeted for a publicly traded company’s flag ship consumer product.

The ASIC controls multiple motors for forward / reverse / variable speed / variable torque operations. Also included are 200 general purpose instrumentation amplified sensor inputs, battery charge management, voltage level sensing, a temperature sensor, an internal RC oscillator, a watchdog timer and an LDO regulator.

The motor operating Voltage range is between 5V to 35V, while the rest of the chip can operate between 3V to 5V. All control and data are available through a 10 MHz SPI bus. The part is packaged in a 68 pin QFN package.

This ASIC is similar to many others designed at Chronicle and CSS. We specialize in custom mixed-signal ASICs for control and instrumentation applications in a variety of markets. Use our contact form if you have any questions or help to decide if a mixed-signal ASIC is right for you and your application.




CSS and Chroncle Technology Merge

February 4th, 2013 by Keith

We have some great news! Custom Silicon Solutions (CSS) and Chronicle Technology’s ASIC division completed a merger as of Jan 1st, 2013. The newly combined company will continue to operate as CSS. The merger greatly increases the design bandwidth and depth of the mixed signal ASIC design capability.

Chronicle’s design team complements the CSS design team with many years of experience designing state-of-the-art, high performance circuits in Digital, Analog, Mixed-Signal, Image Sensor, and RF applications utilizing CMOS, SiGe, BiCMOS, BiPolar, CIS, and SOI process technologies. Foundry experience now includes ON Semi, Tower Jazz, XFab, Atmel, IBM, Global, UMC, SMIC, and TSMC in dimensions from 65 nm to 1.25 micron.

Chronicle Technology has been providing advanced IC designs for 17 years, producing over 200 tape-outs for clients in the Industrial, Medical, Military and Commercial markets.  Coincidentally, CSS has also been in business for about the same time (both were founded in 1996) serving similar markets. CSS has an extensive track record for shipping tested, packaged ASICs, while Chronicle’s team has extensive design expertise in advanced integrated technologies. The new CSS will be able to provide a broader range of Custom Turn-Key ASIC Solutions – from Development through Production.

Keith Shelton is partially retiring while continuing with CSS as a consultant and Board Director.


CSS555 Timer and Demo Kit on YouTube

October 10th, 2012 by Keith

We have recently published a video on YouTube which briefly explains the features of our CSS555 Timer IC and the use of the CSS555 Demonstration Kit for that Timer IC.  Please follow this link and take a look.  If you have an interest in the CSS555 Timer or Demo Kit you may want to use our contact form or visit our website under Standard Products.  Both the CSS555 and the CSS555 Demo Kit are available for purchase from .

CSS employees have a long history in the development and use of non-volatile memory.  Frank Bohac and I began our non-volatile memory work in the late 70’s at the Hughes Research Center in Newport Beach, California.  At that time, Dr. Eli Harari was at the Hughes Newport Research center developing the fundamentals of  EEPROMs using Fowler-Nordheim tunneling to erase and program floating gate non-volatile memories.  Eli was to prove that this fundamental technology was practical for integrated technology.  To prove this, Eli used a tester that I had developed that would easily test thousands of tunnel oxides to establish their characteristics.  Thus, he and I became acquainted and soon afterwards, I began working on the floating gate EEPROM development, as well.  Eli successfully filed many patents establishing this basic technology as practical in the fabrication of floating gate non-volatile memories, with the seminal paper “Dielectric Breakdown in Electrically Stressed Thin Films on Thermal SiO2”. (link: http://dx.doi.org/10.1063/1.325096)  Also, see our earlier Blog (September 2012)  on the IEEE Significant Event Award recently presented to Dr. Harari.

This early EEPROM development was shown in a poster at the Flash Memory Summit recently held in Santa Clara.  Below, a portion of the poster indicates the work completed at the Hughes Research Center from 1976 to 1980.

EEPROM Development at Hughes Research Center

Dr. Tom Tombs, then the director of the Hughes Research Center, asked if I would take this EEPROM technology and develop it to a production level at the Hughes Microelectronics Division (also in Newport Beach).  An 8K bit EEPROM CMOS memory (originally designed by Frank Wanlass under contract by Hughes) was used as a vehicle to prove production capability.

At Hughes Microelectronics, I worked with process development engineers (primarily Bruce Paynter) in a variety of process experiments aimed at improving what was initially a dismal yield on the 8K bit EEPROM.  The primary breakthrough was the realization that Nitrogen used to control the start and termination of the tunnel oxide growth had a detrimental effect on tunnel oxide yield and endurance characteristics.  By removing Nitrogen from the process we were able to significantly improve tunnel oxide yield.  Another significant realization was that the peak magnitude of the tunnel oxide current needed to be carefully controlled to prevent early breakdown of the oxide.   We found that through careful control of the rise time of the voltage used to program the EEPROM we could avoid this oxide damage.

I presented the development of the 8K EEPROM at the Non-volatile Memory Workshop held in 1980 in Vail, Colorado.  The paper was well received with a torrent of questions following the presentation.  I also wrote an article describing the 8K bit EEPROM entitled: “Low-Power EEPROM Can Be Re-programmed Fast” in the July 31, 1980 issue of “Electronics” magazine.  These papers presented an overview of the basic non-volatile functions of these memories.

Frank Bohac joined the development team at Hughes Microelectronics and became the key designer of changes to the CMOS EEPROM.  Frank fixed some problems with the initial EEPROM design which were unrelated to the non-volatile memory (latch-up) and provided memory maps that led us to determine the effects of tunnel oxide shorts on adjacent cells.  However, the first major change was the addition of redundancy to the EEPROM.  Even though yield of the tunnel oxides was reasonably good with the above developments, a large number of devices were failing (due to tunnel oxide failures) either initially or after a few programming cycles.  We determined that just a few bits of redundancy were needed to fabricate the 8K EEPROMs with acceptable yields.  Frank also added internal program voltage generation to the EEPROM.  This internal program voltage generator provided for a nearly ideal voltage rise time which reduced peak tunnel oxide current and hence reduced tunnel oxide failures.  Frank successfully redesigned the 8K EEPROM to include both redundancy and an internal program voltage generator.   These additions brought the EEPROM yields to an acceptable production level.  Frank also presented a paper at a later Nonvolatile Memory Workshop which described the redundancy used in the 8K EEPROM at Hughes as well as the details of the programming voltage generator waveform used in this memory.

We also determined that for reliability it was necessary to repeatedly program and erase the EEPROM prior to sale to remove any tunnel oxides with apparent latent defects. (The failed cells were replaced with good cells via the redundancy circuitry).  Although this was a time consuming and expensive process (10K cycles at 125 degrees C), it was believed necessary (with the quality of oxides at that time) for a high reliability device.  Today, tunnel oxides at our foundries are of much higher quality and such screening techniques are not required.

During this period of time, Hughes won a contract from ERADCOM to evaluate the floating gate non-volatile memory technology available on the market.  Bruce Paynter, Frank Bohac and I performed this work by evaluating the endurance and retention characteristics of EEPROM memories available from Intel, National and Hughes.  This was an in-depth analysis of EEPROMs, establishing for the first time significant data on the technology’s endurance and retention characteristics.   Long term endurance and retention characteristics have not changed a lot since that time as long as the fundamentals of the Fowler-Nordheim tunneling characteristics are observed.

EEPROM development at Hughes continued with a 16K bit EEPROM and a non-volatile RAM IC (NovRAM).  However, EEPROM as a standard product was discontinued following a management change at Hughes.  This change led to the creation of the Custom Design group at Hughes which was chartered to provide custom ICs to Hughes customers – both internal to Hughes and externally.  I led this group to develop mixed signal custom IC’s with a special emphasis on the use of the EEPROM technology.  In these applications, EEPROM technology was used for small amounts of code storage, for configuration purposes, for non volatile counters, and for storing the bits used to trim analog function for higher accuracy.  This group provided these custom ICs to a number of companies, the largest of which was Delco Electronics who used them in dashboard instrumentation applications.  Notable among these was the first solid state odometer using EEPROM technology with endurance capability to remember the odometer reading to over 1 million miles.

As you may have guessed by now, CSS was formed by Frank and I in 1997 based on many of these developments at Hughes Microelectronics Division.  Although the Hughes Microelectronics is now closed, we still provide custom mixed signal IC’s with an emphasis on non-volatile memory (EEPROM) technology to the Industrial, Medical and Military markets.

One of our first jobs in this regard was to design an EEPROM for the C5 process (0.5 micron CMOS) at AMI Semiconductor (Now ON Semiconductor).  Under contract with AMI, CSS developed a basic EEPROM array macro with all the necessary interface circuitry, including a programming voltage generator.   The process at AMI was referred to (internally at AMI) as the “NASTEE” process (No Added Steps To EEprom).  This process with non-volatile memory is still heavily used at ON Semiconductor for mixed-signal ASIC designs.

At the same time we added a very important non-volatile circuit: the Non-volatile Latch.  The NV Latch is a basic latch circuit that always comes up in the programmed state when power is applied.  It is often used in small non-volatile registers as part of a trimming function for analog circuits.   The “Non-volatile Register” is now promoted by ON Semiconductor Foundry Services as IP available from CSS (See the CSS Blog: ON Semi Foundry Services Promotes CSS NV Register: August, 2012).
Since that time, we have designed numerous EEPROM memories and added new versions of the NV Latch Register.  We have doubled the density of the NV Latch Registers and significantly reduced the size of the EEPROM arrays using the same 0.5 micron technology.  We have also improved the performance of the programming voltage generators.  These advanced versions of the original EEPROM technology are available for CSS customers either directly for their own designs or in custom ASIC designs we provide.

At CSS we continue to use this non-volatile memory technology regularly in the design of custom ASICs.  Some notable designs include a non-volatile real time counter in an Industrial application at Curtis Instruments, a custom ASIC with non-volatile memory used for ID purposes in a smart utility meter at Itron, a custom mixed signal ASIC with non-volatile memory for Epitel (Medical) to configure applications and trim analog functions, and an unusual ASIC used to control the temperature of a crystal oscillator for Frequency Electronics.  These are just a few of the many applications at CSS that use the non-volatile memory technology.   It is used in approximately 80% of our custom ASICs.

Recently, we have been working on non-volatile memory macros for more advanced processes, especially the 0.18 micron process (ONC18) at ON Semiconductor Foundry Services.  These new 0.18 micron non-volatile memory macros will serve a function similar to the earlier 0.5 micron cells developed for AMI, but in the more advanced process at ON Semiconductor Foundry Services.
If you would like more information on non-volatile memory and how it might be used to improve performance in a mixed signal CMOS ASIC for your electronic system, please don’t hesitate to give us a call at 949-797-9220 or use our contact form for a written reply.

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