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Frank

Analog Trimming with On-chip EEPROM

March 23rd, 2009 by Frank

 

Most of our mixed signal ASIC designs benefit greatly by including the ability to trim key analog circuits.  These often include an amplifier gain/offset, a bandgap reference voltage, a bias current generator or the frequency of an oscillator or filter.  A small amount of nonvolatile memory, coupled with an array of FET switches, resistors and capacitors can provide the equivalent of a discrete DIP switch, trim pot or trim capacitor.  An integrated version of these components also has the advantage of providing electronic trimming.

The most versatile type of memory for storing a trim setting is an EEPROM (Electrically Erasable Programmable Read Only Memory).  As the name implies, it can be written and erased electrically and therefore allows a trim setting to be changed numerous times, either at device test or in the application circuit.  A conventional EEPROM contains a memory core, surrounded by peripheral circuits (row/column drivers, sense amps, etc.).  It may require significant die area and special process steps, both of which may drive the cost of the IC to unacceptable levels.  What’s really needed for holding a trim setting is a small, efficient EEPROM that does not significantly impact cost.

Our nonvolatile registers provide an ideal solution for storing trim settings.  The core memory circuit is a self-contained, nonvolatile latch (NV Latch).  Each NV Latch includes its own level shifter and sense amp, so they can be distributed anywhere they are needed.  They automatically power up to their last programmed state and draw essentially no static current (just junction leakage current – typically less than 1nA).  They can be mated to a wide variety of digital interface circuits to provide serial and parallel read/write access.

Our NV Latch cell does not require any special processing during wafer fabrication, so including it in a design does not add processing steps (or cost).  Even though each bit is completely self-contained, it is still a very area efficient memory.  In the table below, the area required for conventional and latch based EEPROMs are listed.  As expected, when a large number of bits are required, a conventional EEPROM is the densest configuration.  For applications requiring less than several hundred bits, a latch based architecture can be much smaller (and flexible).  For example, a 16 bit NV register requires under 20 square mils or about 1.08 square mils per bit.  This is about the same density per bit as a 0.5K EEPROM, but can be added in 16 bit increments and distributed throughout the IC.  A conventional EEPROM typically has a minimum size of several hundred square mils, corresponding to 256 to 1K bits.  (As the number of bits is reduced, the peripheral circuits dominate the total area required for the memory, making very small memories impractical.)  When less than 100 bits are required, an NV Register can be more than 10 times smaller than a conventional EEPROM.

 EEPROM Area (Conventional vs. NV Latch)

EEPROM

Size (bits)

Total Area

(sq. mils)

Area/Bit

(sq. mils)

 

NV Latch

Size (bits)

Total Area

(sq. mils)

Area/Bit

(sq. mils)

512

567

1.11

 

8

10.3

1.29

1K

640

0.63

 

16

17.3

1.08

2K

790

0.39

 

24

24.3

1.01

4K

1080

0.26

 

32

31.3

0.98

8K

1670

0.20

 

48

45.2

0.94

16K

2850

0.17

 

64

59.1

0.92

32K

5240

0.16

 

128

116.5

0.91

If you are an IC designer and would like to explore the features of our NV Registers for your own design, you can download specifications for our “Classic” and “High Density” macro cells.  Calculators for our latch based and conventional EEPROMs are also available.  (These are interactive tools that provide EEPROM area estimates for different memory configurations.)  You can download specifications and calculators by visiting our Products/IP Products web page.  Look for “16K EEPROM”, “High Density NV Register” and “NV Register” (Classic Version).

Our library of NV Registers provide a very versatile memory for storing analog trim settings.  Because they require minimal area and no extra processing steps, they have little or no impact on part cost, but can significantly improve part performance.  (They often reduce cost by improving yield when a spec is tight.)  We have found these small EEPROMs so useful that almost all of our mixed signal designs use them.  In addition to storing trim settings, we often use them to save counter states (odometers), configuration data and part ID’s.  For more examples of typical applications, see our “Products/Applications Overview” web page.

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