CSS Mixed Signal ASIC Solutions

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CSS employees have a long history in the development and use of non-volatile memory.  Frank Bohac and I began our non-volatile memory work in the late 70’s at the Hughes Research Center in Newport Beach, California.  At that time, Dr. Eli Harari was at the Hughes Newport Research center developing the fundamentals of  EEPROMs using Fowler-Nordheim tunneling to erase and program floating gate non-volatile memories.  Eli was to prove that this fundamental technology was practical for integrated technology.  To prove this, Eli used a tester that I had developed that would easily test thousands of tunnel oxides to establish their characteristics.  Thus, he and I became acquainted and soon afterwards, I began working on the floating gate EEPROM development, as well.  Eli successfully filed many patents establishing this basic technology as practical in the fabrication of floating gate non-volatile memories, with the seminal paper “Dielectric Breakdown in Electrically Stressed Thin Films on Thermal SiO2”. (link: http://dx.doi.org/10.1063/1.325096)  Also, see our earlier Blog (September 2012)  on the IEEE Significant Event Award recently presented to Dr. Harari.

This early EEPROM development was shown in a poster at the Flash Memory Summit recently held in Santa Clara.  Below, a portion of the poster indicates the work completed at the Hughes Research Center from 1976 to 1980.

EEPROM Development at Hughes Research Center

Dr. Tom Tombs, then the director of the Hughes Research Center, asked if I would take this EEPROM technology and develop it to a production level at the Hughes Microelectronics Division (also in Newport Beach).  An 8K bit EEPROM CMOS memory (originally designed by Frank Wanlass under contract by Hughes) was used as a vehicle to prove production capability.

At Hughes Microelectronics, I worked with process development engineers (primarily Bruce Paynter) in a variety of process experiments aimed at improving what was initially a dismal yield on the 8K bit EEPROM.  The primary breakthrough was the realization that Nitrogen used to control the start and termination of the tunnel oxide growth had a detrimental effect on tunnel oxide yield and endurance characteristics.  By removing Nitrogen from the process we were able to significantly improve tunnel oxide yield.  Another significant realization was that the peak magnitude of the tunnel oxide current needed to be carefully controlled to prevent early breakdown of the oxide.   We found that through careful control of the rise time of the voltage used to program the EEPROM we could avoid this oxide damage.

I presented the development of the 8K EEPROM at the Non-volatile Memory Workshop held in 1980 in Vail, Colorado.  The paper was well received with a torrent of questions following the presentation.  I also wrote an article describing the 8K bit EEPROM entitled: “Low-Power EEPROM Can Be Re-programmed Fast” in the July 31, 1980 issue of “Electronics” magazine.  These papers presented an overview of the basic non-volatile functions of these memories.

Frank Bohac joined the development team at Hughes Microelectronics and became the key designer of changes to the CMOS EEPROM.  Frank fixed some problems with the initial EEPROM design which were unrelated to the non-volatile memory (latch-up) and provided memory maps that led us to determine the effects of tunnel oxide shorts on adjacent cells.  However, the first major change was the addition of redundancy to the EEPROM.  Even though yield of the tunnel oxides was reasonably good with the above developments, a large number of devices were failing (due to tunnel oxide failures) either initially or after a few programming cycles.  We determined that just a few bits of redundancy were needed to fabricate the 8K EEPROMs with acceptable yields.  Frank also added internal program voltage generation to the EEPROM.  This internal program voltage generator provided for a nearly ideal voltage rise time which reduced peak tunnel oxide current and hence reduced tunnel oxide failures.  Frank successfully redesigned the 8K EEPROM to include both redundancy and an internal program voltage generator.   These additions brought the EEPROM yields to an acceptable production level.  Frank also presented a paper at a later Nonvolatile Memory Workshop which described the redundancy used in the 8K EEPROM at Hughes as well as the details of the programming voltage generator waveform used in this memory.

We also determined that for reliability it was necessary to repeatedly program and erase the EEPROM prior to sale to remove any tunnel oxides with apparent latent defects. (The failed cells were replaced with good cells via the redundancy circuitry).  Although this was a time consuming and expensive process (10K cycles at 125 degrees C), it was believed necessary (with the quality of oxides at that time) for a high reliability device.  Today, tunnel oxides at our foundries are of much higher quality and such screening techniques are not required.

During this period of time, Hughes won a contract from ERADCOM to evaluate the floating gate non-volatile memory technology available on the market.  Bruce Paynter, Frank Bohac and I performed this work by evaluating the endurance and retention characteristics of EEPROM memories available from Intel, National and Hughes.  This was an in-depth analysis of EEPROMs, establishing for the first time significant data on the technology’s endurance and retention characteristics.   Long term endurance and retention characteristics have not changed a lot since that time as long as the fundamentals of the Fowler-Nordheim tunneling characteristics are observed.

EEPROM development at Hughes continued with a 16K bit EEPROM and a non-volatile RAM IC (NovRAM).  However, EEPROM as a standard product was discontinued following a management change at Hughes.  This change led to the creation of the Custom Design group at Hughes which was chartered to provide custom ICs to Hughes customers – both internal to Hughes and externally.  I led this group to develop mixed signal custom IC’s with a special emphasis on the use of the EEPROM technology.  In these applications, EEPROM technology was used for small amounts of code storage, for configuration purposes, for non volatile counters, and for storing the bits used to trim analog function for higher accuracy.  This group provided these custom ICs to a number of companies, the largest of which was Delco Electronics who used them in dashboard instrumentation applications.  Notable among these was the first solid state odometer using EEPROM technology with endurance capability to remember the odometer reading to over 1 million miles.

As you may have guessed by now, CSS was formed by Frank and I in 1997 based on many of these developments at Hughes Microelectronics Division.  Although the Hughes Microelectronics is now closed, we still provide custom mixed signal IC’s with an emphasis on non-volatile memory (EEPROM) technology to the Industrial, Medical and Military markets.

One of our first jobs in this regard was to design an EEPROM for the C5 process (0.5 micron CMOS) at AMI Semiconductor (Now ON Semiconductor).  Under contract with AMI, CSS developed a basic EEPROM array macro with all the necessary interface circuitry, including a programming voltage generator.   The process at AMI was referred to (internally at AMI) as the “NASTEE” process (No Added Steps To EEprom).  This process with non-volatile memory is still heavily used at ON Semiconductor for mixed-signal ASIC designs.

At the same time we added a very important non-volatile circuit: the Non-volatile Latch.  The NV Latch is a basic latch circuit that always comes up in the programmed state when power is applied.  It is often used in small non-volatile registers as part of a trimming function for analog circuits.   The “Non-volatile Register” is now promoted by ON Semiconductor Foundry Services as IP available from CSS (See the CSS Blog: ON Semi Foundry Services Promotes CSS NV Register: August, 2012).
Since that time, we have designed numerous EEPROM memories and added new versions of the NV Latch Register.  We have doubled the density of the NV Latch Registers and significantly reduced the size of the EEPROM arrays using the same 0.5 micron technology.  We have also improved the performance of the programming voltage generators.  These advanced versions of the original EEPROM technology are available for CSS customers either directly for their own designs or in custom ASIC designs we provide.

At CSS we continue to use this non-volatile memory technology regularly in the design of custom ASICs.  Some notable designs include a non-volatile real time counter in an Industrial application at Curtis Instruments, a custom ASIC with non-volatile memory used for ID purposes in a smart utility meter at Itron, a custom mixed signal ASIC with non-volatile memory for Epitel (Medical) to configure applications and trim analog functions, and an unusual ASIC used to control the temperature of a crystal oscillator for Frequency Electronics.  These are just a few of the many applications at CSS that use the non-volatile memory technology.   It is used in approximately 80% of our custom ASICs.

Recently, we have been working on non-volatile memory macros for more advanced processes, especially the 0.18 micron process (ONC18) at ON Semiconductor Foundry Services.  These new 0.18 micron non-volatile memory macros will serve a function similar to the earlier 0.5 micron cells developed for AMI, but in the more advanced process at ON Semiconductor Foundry Services.
If you would like more information on non-volatile memory and how it might be used to improve performance in a mixed signal CMOS ASIC for your electronic system, please don’t hesitate to give us a call at 949-797-9220 or use our contact form for a written reply.

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