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Custom Silicon Solutions (CSS) has just released SPICE simulation models for our CSS555 and CSS555C ICs.  These models provide a simulation capability at the component level.  To make them portable across many simulators, only Level 1 device models are used.  The voltage comparators are modeled with BLM gain blocks to reduce simulation time.  Even with these simplifications, the model provides a very good representation of the real IC.


The CSS 555 Timer model includes:

   1) Supply Current (over VDD)

2) Input Switch Levels

3) Propagation Delay Time

4) Output Drive (over temperature and VDD)

5) ESD Clamp Diodes and Pad Capacitance

The power and trip level settings (stored in EEPROM) change the IC’s supply current, propagation delay and trip level parameters.  Separate SPICE model files are provided for each combination of power and trip level settings.

CSS 555 SPICE Model

The CSS555 SPICE model has been structured to provide an accurate model that runs quickly and is compatible with most SPICE simulators.  It includes the analog portion of the IC and covers most of the important electrical characteristics, including supply current, input levels, output drive and propagation delay.  The model can be used over a wide operating range: VDD = 1.2V to 5.5V, Temperature = -40°C to 85°C.  Most of the device parameters are valid across this range.  Models for different configuration settings (power & trip levels) are also provided, along with tables to adjust the models for worst-case conditions.  Complete details are provided in Application Note 555-2 “CSS555 SPICE Model”.


One Response to “Spice Models for CSS’s 555 Timer are Now Available”

  1. This chip is great and I know the SPICE module will be too.
    Best regards